Optimizing Neural Network Representations of Boolean Networks
Authors: Joshua Russell, Ignacio Gavier, Devdhar Patel, Edward Rietman, Hava Siegelmann
ICLR 2025 | Venue PDF | Archive PDF | Plain Text | LLM Run Details
| Reproducibility Variable | Result | LLM Response |
|---|---|---|
| Research Type | Experimental | We demonstrate experimentally that we are able to reduce connections and neurons by up to 70% and 60%, respectively, in comparison to state-of-the-art. We also find that our objective-aware algorithm results in consistent speedups in optimization time, achieving up to 34.3 and 5.9 speedup relative to naive and caching solutions, respectively. Our methods are of practical relevance to applications such as high-throughput circuit simulation and placing neurosymbolic systems on the same hardware architecture. ... Our experimental results demonstrate that our methods lead to significant optimization in NN size, as well as consistent speedups in the optimization process. |
| Researcher Affiliation | Academia | Joshua Russell Ignacio Gavier Devdhar Patel Edward Rietman Hava T. Siegelmann University of Massachusetts Amherst EMAIL |
| Pseudocode | Yes | Algorithm 1: MPand MMP-based technology mapping with NPN classes ... Algorithm 2: Maintain depth NN optimization algorithm (opt Maintain Depth) ... Algorithm 3: Computing leeways ... Algorithm 4: Augmenting a BN with a temporary vertex |
| Open Source Code | No | The paper does not provide an explicit statement of code release, a link to a repository for the described methodology, or mention that code is provided in supplementary materials. |
| Open Datasets | Yes | We provide additional information and references for the four open-source digital circuits used in the experimental results of the main text. uart4 is a communications core... sha35 is a cryptographic core... ecg6 is a cryptographic core... aes7 is a cryptographic core... 4https://opencores.org/projects/uart2bus 5https://opencores.org/projects/sha3 6https://opencores.org/projects/ecg 7https://opencores.org/projects/tiny_aes |
| Dataset Splits | No | The paper evaluates optimization algorithms on Boolean networks derived from digital circuits and DFAs, which are not typically partitioned into training, validation, and test sets in the context of this research. No specific dataset split information is provided. |
| Hardware Specification | Yes | Experiments were conducted on an Intel(R) Xeon(R) Gold 6230R CPU @ 2.10GHz with 196 GB RAM. |
| Software Dependencies | No | The paper states: "We use the algorithm proposed by Zhou et al. (2020) to compute NPN transformations and canonical forms." This refers to a specific algorithm from a published work, not a software library or tool with a version number used in their own implementation. |
| Experiment Setup | Yes | We evaluate the proposed architectureand objective-aware optimization algorithms on four BNs derived from digital circuits: uart, sha3, ecg, and aes (see Appendix F for details). ... Experiments were conducted on an Intel(R) Xeon(R) Gold 6230R CPU @ 2.10GHz with 196 GB RAM. ... We report the optimization time for MPand MMP-based technology mapping w.r.t. the uniform (cuni) and degree (cdeg) criterions. ... Lines and error bars denote sample mean and standard deviation over 3 trials. Circuit sizes are shown in parentheses in terms of number of logic gates. |