Notice: The reproducibility variables underlying each score are classified using an automated LLM-based pipeline, validated against a manually labeled dataset. LLM-based classification introduces uncertainty; scores should be interpreted as estimates. Full accuracy metrics and methodology are described in [1]
Computing Hierarchical Finite State Controllers With Classical Planning
Authors: Javier Segovia-Aguas, Sergio Jiménez, Anders Jonsson
JAIR 2018 | Venue PDF | LLM Run Details
| Reproducibility Variable | Result | LLM Response |
|---|---|---|
| Research Type | Experimental | Section 6. Evaluation: This section evaluates the performance of our approach for the computation of FSCs in a selection of generalized planning benchmarks... Table 1 summarizes the obtained results when using our compilation to compute controllers for the introduced benchmarks. ... Last but not least we report, for each domain, the planning time and plan length required by the classical planners Fast Downward and Best-First Width Search to compute the controllers. |
| Researcher Affiliation | Academia | Javier Segovia-Aguas EMAIL Dept. Information and Communication Technologies Universitat Pompeu Fabra Roc Boronat 138, 08018 Barcelona, Spain. Sergio Jim enez EMAIL Dept. Sistemas Inform aticos y Computaci on Universitat Polit ecnica de Val encia Camino de Vera s/n. 46022 Valencia, Spain. Anders Jonsson EMAIL Dept. Information and Communication Technologies Universitat Pompeu Fabra Roc Boronat 138, 08018 Barcelona, Spain. |
| Pseudocode | No | The paper describes the actions and their preconditions/effects in a structured textual format within the compilation descriptions (e.g., in Sections 3.2 and 4.3), but it does not present these as explicit 'Pseudocode' or 'Algorithm' blocks. |
| Open Source Code | No | The paper does not contain any explicit statement about releasing the source code for their methodology, nor does it provide a link to a code repository. Appendix A provides PDDL domain and problem definitions, which are input/output formats, not the implementation code for the compilation or the planners used. |
| Open Datasets | Yes | Section 6.1 Experimental Setup and Benchmarks: All experiments are run on a processor Intel Core i7 2.60GHz x 4 with a 4GB memory bound and time limit of 3600s. FSCs are computed solving the corresponding classical planning problem that results from our compilation. ... We briefly describe here each of the evaluation benchmarks. In the An Bn domain the goal is to compute a controller to parse any string consisting of n A s followed by n B s. In Blocks, the goal is to compute a controller that unstack blocks from a single tower until a green block is found. ... These benchmarks are taken from Bonet et al. (2010), Srivastava et al. (2011) and Segovia-Aguas et al. (2016a). Additionally, Appendix A provides PDDL domain and problem files (Figures 6, 7), which serve as explicit definitions for the datasets used in the An Bn problem. |
| Dataset Splits | No | The paper evaluates on classical planning problems and generalized planning benchmarks (Section 6.1), which typically consist of a set of problem instances rather than a single dataset split into train/test/validation. The paper mentions evaluating performance based on 'orderings of the given input instances' (Section 6.3), which implies using different subsets or sequences of problem instances, but not a formal train/test/validation split in the machine learning sense. |
| Hardware Specification | Yes | Section 6.1 Experimental Setup and Benchmarks: All experiments are run on a processor Intel Core i7 2.60GHz x 4 with a 4GB memory bound and time limit of 3600s. |
| Software Dependencies | No | Section 6.1 Experimental Setup and Benchmarks: The classical planning problems output by our compilation are solved running the following two classical planners: 1. Fast Downward (Helmert, 2006) with the Lama-2011 setting (Richter & Westphal, 2010). 2. Best-First Width Search with the Dual-BFWS setting (Lipovetzky & Geffner, 2017). While specific planners and settings are mentioned, explicit version numbers for these software components are not provided. |
| Experiment Setup | Yes | Section 6.1 Experimental Setup and Benchmarks: All experiments are run on a processor Intel Core i7 2.60GHz x 4 with a 4GB memory bound and time limit of 3600s. Section 4.3 Computing Hierarchical Finite State Controllers: The parameters of the compilation are n, a bound on the number of controller states, m that is a bound on the number of FSCs and ℓ, a bound on the stack size. |